This application claims the benefit of the Korean Application No. P2003-38530 filed on Jun. 14, 2003, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor test handlers for testing semiconductor devices.
2. Background of the Related Art
In general, after production of semiconductor devices such as, for example, memory or non-memory devices and modules having semiconductor devices mounted on a board to form a circuit, the semiconductor devices and modules are tested before shipment using a semiconductor test handler. Many of the semiconductor test handlers are designed to carry out not only general performance tests at room temperature, but also high temperature tests and low temperature tests. The temperature tests may include an extreme temperature state of high temperature or low temperature formed by using an electric heater or a liquefied nitrogen spray system, respectively, in an enclosed chamber. The semiconductor device or the module may be tested under such temperature extremes whether or not the semiconductor device or the module is normally operated in such an extreme temperature condition.
FIGS. 1-3 illustrate exemplary systems of a semiconductor test handler or handler provided with loading stackers 10 in a front part of the handler for stacking user trays each having a plurality of semiconductor devices S to be tested thereon. The semiconductor test handler also includes unloading stackers 20 on one side of the loading stackers 10 having a stack of user trays. Each user tray has tested semiconductor devices S put thereon classified according to a result of a test.
On opposite parts of a middle part of the handler, there are buffer parts 40. Each buffer part 40 is mounted to be movable in front and rear directions for temporary mounting of the semiconductor devices S transferred from the loading stacker 10. In a center part of the middle part of the handler is an exchange part 50 for mounting the semiconductor device S to be tested. The semiconductor device S to be tested may be additionally transferred from the buffer part 40 on a test tray T. Such a transfer requires mounting the tested semiconductor device S mounted on the test tray T on the buffer part 40.
The handler also includes first pickers 31 and second pickers 32 between the front part having the loading stackers 10 and the unloading stackers 20 provided thereto. The first pickers 31 and second pickers 32 are also located in the middle part of the handler having the exchange part 50 and the buffet parts 40. The first pickers 31 and second pickers 32 are for making linear movement in X-axis, and Y-axis directions, and for picking up and transporting the semiconductor devices S. The first pickers 31 may access the loading stackers 10, the unloading stackers 20, and the buffers 40. The second pickers 32 may access the buffer part 40 and the exchange part 50 for picking up and transporting the semiconductor devices S.
In a rear part of the handler is a test site 70 having a plurality of enclosed chambers including a pre-heating chamber 71, a test chamber 72, and a defrosting chamber 73. The chambers are arranged for moving the test tray T having the semiconductor device S mounted thereon between them in a sequence after the high temperature or low temperature environment is formed therein. The chambers are for testing a performance of the semiconductor device S under test temperature conditions.
FIGS. 2 and 3 illustrate alignment shuttles 51 in the exchange part 50. The alignment shuttles 51 are for aligning the semiconductor devices S with spacing similar to the pitch in a device mounting carrier in the test tray T. The alignment shuttle 51 has a plurality of device seating blocks 51a arranged at regular intervals. The intervals are similar to the pitches in the carrier. The alignment shuttles 51 are designed to be movable back and forth to positions on the handler base under the test tray T and the second pickers 32. The alignment shuttles 51 are for receiving the semiconductor devices S on an upper surface of the device seating block 51a, and transferring aligned semiconductor devices S between the test tray T and the second picker 32.
There is a lower pushing unit under the exchange part 50. The lower pushing unit moves up the alignment shuttle 51 to mount the semiconductor devices S on the alignment shuttle 51 on the test tray T. The semiconductor device S is preferably arranged horizontally. Disposed over the exchange part 50 is an upper pushing unit for separating the semiconductor devices S from carriers on an upper side of the test tray T and mounting the semiconductor devices S back on the alignment shuttle 51. The lower pushing unit has a nozzle part 200 configured to come into contact with a bottom of the device seating block 51a and move the alignment shuttle 51 up or down. The nozzle part 200 is also configured to draw air through the through-hole 51b in the device seating block 51a for sensing positive seating of the semiconductor devices S.
Referring to FIG. 3, when the semiconductor device S is seated on the device seating block 51a of the alignment shuttle 51, a seating error may occur. Seating errors may be caused by dust or other debris or obstructions on a seating surface of the device seating block 51a or the semiconductor devices S being tilted or otherwise misaligned on the seating surface. A gap between the semiconductor device S and the seating surface results when there is a seating error. Such a gap may cause air leakage therethrough, and failure of a vacuum tight seal to form will occur. A handler control unit determines when a semiconductor device S is not seated properly, and stops operation of the handler for a worker to confirm a seating error when improper alignment is sensed. A stop of the handler operation caused by any false seating error, such as a misalignment sensing error, leads to a drop of productivity as well as reduced work efficiency of the worker as the test is delayed during the stopped time period.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Accordingly, the present invention is directed to a device for seating a semiconductor device in a semiconductor test handler that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a device for seating a semiconductor device in a semiconductor test handler which can make an accurate and positive seating of the semiconductor device on a seating device.
Another objection of the present invention is to provide a device for seating a semiconductor device in a semiconductor test handler for accurate and positive seating of the semiconductor device on a seating surface.
A further object of the present invention is to provide a device aligning shuttle for alignment of a semiconductor device before the semiconductor device is transferred to a required working position in a semiconductor test handler.
To achieve these objects and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, a device for seating a semiconductor device in a semiconductor test handler includes a plate having a plurality of device seating members each for seating the semiconductor device, a latch rotatably mounted to one side of the device seating member for pressing down or freeing the semiconductor device seated on the device seating member, and latch operating means for making the latch to press down the semiconductor device in a state the semiconductor device is seated on the device seating member, and to release the pressing down action when the semiconductor device is seated on the device seating member, and when the semiconductor device is taken away from the device seating member.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.